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Integrated Circuit Systems, Inc.
ICS9159-13
Frequency Generator and Integrated Buffer for PENTIUM
The ICS9159-13 generates all clocks required for high speed RISC or CISC microprocessor systems such as 486, Pentium, PowerPC,TM etc. Four different reference frequency multiplying factors are externally selectable with smooth frequency transitions. A test mode is provided to drive all clocks directly. High drive BCLK outputs provide typically greater than 1V/ns slew rate into 30pF loads. PCLK outputs provide typically better than 1V/ns slew rate into 20pF loads while maintaining 505% duty cycle.
General Description

Features
Generates up to six processor and six bus clocks, plus two reference clocks Synchronous clocks skew matched to 250ps window on PCLKs and 500ps window on BCLKs Processor and bus clocks synchronized to each other, PCLK to BCLK skew window 600ps max Test clock mode eases system design 3.0V - 5.5V supply range 28-pin SOIC package
Block Diagram
Pin Cnfiguration
28-Pin SOIC Functionality
OEN 1 1 1 1 0 FS1 0 0 1 1 X FS0 0 1 0 1 X PCLK 50MHz 66.6 MHz 60 MHz TCLK/2 Tristate BCLK 25 MHz 33.3 MHz 30 MHz TCLK/4 Tristate REF 14.318 MHz 14.318 MHz 14.318 MHz TCLK Tristate
Pentium is a trademark of Intel Corporation. PowerPC is a trademark of Motorola Corporation. 9159-13 Rev B 060497
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9159-13
Pin Descriptions
PIN NUMBER 1, 8, 14, 20, 26 2 3 4, 11, 17, 23 6, 7, 9, 10, 24, 25 13, 12 15, 16, 18, 19, 21, 22 5 28, 27 PIN NAME VDD X1 X2 GND PCLK(0:3) FS(0:1) BCLK(0:5) OEN REF(0:1) TYPE PWR IN OUT PWR OUT IN OUT IN OUT DESCRIPTION Power for logic, CPU and fixed frequency output buffers. XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12 - 16 MHz crystal, nominally 14.31818 MHz. XTAL output which includes XTAL load capacitance. Ground for logic, CPU and fixed frequency output buffers. Processor clock outputs which are a multiple of the input reference frequency as shown in the table above. Frequency multiplier select pins. See table above. These inputs have internal pull-up devices. Bus clock outputs are fixed at one half the PCLK frequency. OEN tristates all outputs when low. This input has an internal pull-up device. REF is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 MHz.
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ICS9159-13
Absolute Maximum Ratings
Supply Voltage .......................................................................................................... 7.0 V Logic Inputs ....................................................................... GND 0.5 V to VDD +0.5 V Ambient Operating Temperature ............................................................. 0C to +70C Storage Temperature ........................................................................... 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 3.7 V, TA = 0 70 C unless otherwise stated
DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current1 Output High Current
1
SYMBOL VIL VIH IIL IIH IOL IOH IOL IOH VOL VOH VOL VOH IDD VIN=0V
TEST CONDITIONS
MIN 0.7VDD -28.0 -5.0 30.0 25.0 2.4 2.4 -
TYP -10.5 47.0 -66.0 38.0 -47.0 0.3 2.8 0.3 2.8 55
MAX 0.2VDD 5.0 -42.0 -30.0 0.4 0.4 110
UNITS V V A A mA mA mA mA V V V V mA
VIN=VDD VOL=0.8V; for PCLKS & BCLKS VOL=2.0V; for PCLKS & BCLKS VOL=0.8V; for REF CLKs VOL=2.0V; for REF CLKs IOL=15mA; for PCLKS & BCLKS IOH=-30mA; for PCLKS & BCLKS IOL=12.5mA; for REF CLKs IOH=-20mA; for REF CLKs @66.5 MHz; all outputs unloaded
Output Low Current1 Output High Current
1
Output Low Voltage1 Output High Voltage
1
Output Low Voltage1 Output High Voltage1 Supply Current
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159-13
Electrical Characteristics at 3.3V
VDD = 3.1 3.7 V, TA = 0 70 C
AC Characteristics PARAMETER Rise Time Rise Time Fall Time
1
SYMBOL Tr1 Tf1 Tr2 Tf2
TEST CONDITIONS 20pF load, 0.8 to 2.0V PCLK & BCLK 20pF load, 2.0 to 0.8V PCLK & BCLK 20pF load, 20% to 80% PCLK & BCLK 20pF load, 80% to 20% PCLK & BCLK 20pF load @ VOUT=1.4V PCLK & BCLK Clocks; Load=20pF, FOUT>25 MHz PCLK & BCLK Clocks; Load=20pF, FOUT>25 MHz REF CLK; Load=20pF REF CLK; Load=20pF Logic input pins X1, X2 pins From VDD=1.6V to 1 st crossing of 66.5 MHz VDD supply ramp < 40ms From 1st crossing of acquisition to < 1% settling PCLK to PCLK; Load=20pF; @1.4V BCLK to BCLK; Load=20pF; @1.4V PCLK to BCLK; Load=20pF; @1.4V
MIN 45 -250 -5 12.0 -
TYP 0.9 0.8 1.5 1.4 50 50 1 2 14.318 5 18 2.5 2.0 150 300 400
MAX 1.5 1.4 2.5 2.4 55 150 250 3 5 16.0 4.5 4.0 250 500 600
UNITS ns ns ns ns % ps ps % % MHz pF pF ms ms ps ps ps
Fall Time1
1 1 1
Duty Cycle
Dt Tj1s1 Tjab1
1
Jitter, One Sigma1 Jitter, Absolute1 Jitter, One Sigma Jitter, Absolute
1 1
Tj1s2 Tjab2 Fi CIN
1
Input Frequency
Logic Input Capacitance1 Crystal Oscillator Capacitance Power-on Time1 Frequency Settling Time 1 Clock Skew Window1 Clock Skew Window Clock Skew Window
1 1
CINX ton ts Tsk1 Tsk2 Tsk3
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159-13
Electrical Characteristics at 5.0V
VDD = 4.5 5.5 V, TA = 0 70 C
DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current1 Output High Current 1 Output Low Current1 Output High Current 1 Output Low Voltage
1
SYMBOL VIL VIH IIL IIH IOL IOH IOL IOH VOL VOH VOL VOH IDD VIN=0V
TEST CONDITIONS
MIN 2.4 -45 -5.0 36.0 30.0 2.4 2.4 -
TYP -15 62.0 -152 50.0 -110.0 0.25 4.0 0.2 4.7 80.0
MAX 0.8 5.0 -90.0 -65.0 0.4 0.4 160.0
UNITS V V A A mA mA mA mA V V V V mA
VIN=VDD VOL=0.8V; for PCLKS & BCLKS VOL=2.0V; for PCLKS & BCLKS VOL=0.8V; for REF CLKs VOL=2.0V; for REF CLKs IOL=20mA; for PCLKS & BCLKS IOH=-70mA; for PCLKS & BCLKS IOL=15mA; for REF CLKs IOH=-50mA; for REF CLKs @66.5 MHz; all outputs unloaded
Output High Voltage1 Output Low Voltage
1
Output High Voltage1 Supply Current
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159-13
Electrical Characteristics at 5.5V
VDD = 4.5 5.5 V, TA = 0 70 C
AC Characteristics PARAMETER Rise Time Fall Time
1 1 1
SYMBOL Tr1 Tf1 Tr2 Tf2
TEST CONDITIONS 20pF load, 0.8 to 2.0V PCLK & BCLK 20pF load, 2.0 to 0.8V PCLK & BCLK 20pF load, 20% to 80% PCLK & BCLK 20pF load, 80% to 20% PCLK & BCLK 20pF load @ VOUT=1.4V 20pF load @ VOUT=50% PCLK & BCLK Clocks; Load=20pF, RS=33W FOUT>25 MHz PCLK & BCLK Clocks; Load=20pF, RS=33W FOUT>25 MHz REF CLKs; Load=20pF RS=33W REF CLKs; Load=20pF RS=33W
MIN 52 45 -250 -5 12.0
TYP 0.55 0.52 1.2 1.1 57 50 50 1 2 14.318 5 18 2.5 2.0 150 300 400
MAX 0.95 0.90 2.1 2.0 62 55 150 250 3 5 16.0 4.5 4.0 250 500 600
UNITS ns ns ns ns % % ps ps % % MHz pF pF ms ms ps ps ps
Rise Time
Fall Time1 Duty Cycle Duty Cycle
1 1
Dt1 Dt2 Tj1s1 Tjab1
1
Jitter, One Sigma1 Jitter, Absolute1 Jitter, One Sigma Jitter, Absolute
1 1 1 1
Tj1s2 Tjab2 Fi CIN CINX ton ts Tsk1 Tsk2 Tsk3
Input Frequency
Logic Input Capacitance
Logic input pins X1, X2 pins From VDD=1.6V to 1 st crossing of 66.5 MHz VDD supply ramp < 40ms From 1st crossing of acquisition to < 1% settling PCLK to PCLK; Load=20pF; @1.4V BCLK to BCLK; Load=20pF; @1.4V PCLK to BCLK; Load=20pF; @1.4V
-
Crystal OscillatorCapacitance Power-on Time
1
Frequency Settling Time1 Clock Skew Window1 Clock Skew Window
1
Clock Skew Window1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159-13
LEAD COUNT DIMENSIONL
28L 0.704
SOIC Package Ordering Information
ICS9159M-13
Example:
ICS XXXX M-PPP
Pattern Number(2 or 3 digit number for parts with ROM code patterns) Package Type
M=SOIC, SOP
Device Type (consists of 3 or 4 digit numbers) Prefix
ICS=Standard Device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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